I2C Protocol Analyzer

TThe CAS-1000-I2C/E™ has all the power, flexibility, and features needed to debug, validate, and test the I2C bus circuitry on a printed circuit board. It is an advanced instrument used in the monitoring and testing of boards and systems incorporating one or more I2C communication busses. The CAS-1000-I2C/E can be used to monitor and log I2C bus traffic in real-time, generate I2C transactions to exercise the bus and communicate to its components, in-system programming of I2C EEPROMs, validate bus specification compliance, confirm I2C protocol of bus traffic, and emulate I2C-compatible devices that are not yet physically connected to the bus. It further complies with the SMbus (System Management Bus) standard variant. The CAS-1000-I2C/E also includes a JTAG controller that, when used with the optional Corelis ScanExpress™ software, can perform structural boundary-scan testing and in-system programming of flash memories and CPLDs.

 

CAS-1000-I2C/E Analyzer

Because of its rich feature set, reliability, portability and ease-of-use, the CAS-1000-I2C/E can be used in a wide variety of applications, such as product development, troubleshooting, validation, system integration, production, and field testing. Windows® XP/Vista/7 host software included with the CAS-1000-I2C/E provides a user-friendly GUI control and visibility of the CAS-1000-I2C/E, including set-up, options, traffic visibility screens, and test actions. For integrating the CAS-1000-I2C/E into a new or existing test environment, the API included with the CAS-1000-I2C/E can be used to operate the CAS-1000-I2C/E from third party software applications such as National Instruments' LabWindows/CVI and LabView software.

Features:
  • Supports I2C and SMBus.
  • Easily connects to PCs and workstations via USB 2.0 interface.
  • Supports Standard-mode, Fast-mode, and Fast-mode Plus (Fm+) with I2C bit rates of up to 5 Mbit/sec.
  • Supports High-speed mode (Hs-mode) monitoring of up to 5 Mbit/sec.
  • Supports I2C Bus Compliance Validation (up to version 2.1), including electrical/timing characteristics, I2C protocol conformance, error trapping/reporting, rise7fall waveform capture/display.
  • Passive traffic monitoring/recording (both state and timing displayed) with time-stamping, message filtering, and symbolic translating.
  • Continuous logging data to disk files.
  • Programmable trigger event to highlight bus transactions of interest and/or signal target or external instrument.
  • Active programmable and interactive traffic generation supporting all modes including Master, Multi-Master, and Slave while emulating up to 1 Master and/or up to 10 Slaves concurrently.
  • Forced I2C error injection can be programmed in the outgoing stream.
  • Programmable bus reference (or floating when target references) and inout threshold voltages.
  • Programmable bus pull-up resistors on SDA and SCL lines ranging from 250 to 50K ohms (or floating when target pulls up).
  • 32/64-Bit Windows® XP/Vista/7 software with an intuitive Graphical User Interface.
  • Powerful command/script language for testing/emulation control.
  • In-System I2C Programming of Serial EEPROMs DLL for intergration to test programs and executives.

Data sheet

CAS-1000 Whitepaper

Software

Major Funcations of CAS-1000-I2C/E:
  • I2C Monitor
  • I2C Emulator
  • I2C Tester
  • I2C Debugger
  • I2C Programmer
  • I2C Parameters Scope

 

SMBus Support

The System Management Bus, or SMBus, was defined by Intel® Corporation in 1995 and is based on the I2C bus architecture. It is used in personal computers and servers for low-speed system management communications.

SMBus is a two-wire interface through which simple system and power management related chips can communicate with the rest of the system. A system using SMBus as a control bus for these system and power management related tasks passes messages to and from devices by addressed transfers, enabling moderate transfer rates using minimal board resources. With System Management Bus, for example, a device can provide manufacturer information, tell the system what its model/part number is, save its state for a suspend event, report different types of errors, accept control parameters, and return its status. The SMBus may share the same host device and physical bus with standard I2C components. Intel originally conceived the SMBus as the communication bus to accommodate Smart Batteries and other system and power management components.

The CAS-1000-I2C/E software features SMBus decoding for common SMBus devices. Ordinarily, the raw data of the I2C transactions between SMBus devices must be manually decoded into meaningful information. With the SMBus decoding feature, a specific device address can be associated with a text file containing decoding information which allows the I2C Exerciser software to do the interpretation automatically.